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MIPS R10000
A case study in modern microarchitecture
Overview
Stage 1: Fetch
Stage 2: Decode/Rename
Branch prediction
Branch predictor
Register renaming
Preparing to issue
Stage 3: Issue
Load-dependents
Functional units
Result writeback
Retirement or commit |
[Reference: K. C. Yeager. The MIPS R10000 Superscalar Microprocessor. IEEE Micro, 16(2): 28-40, April 1996.]
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