Module 18: "TLP on Chip: HT/SMT and CMP"
  Lecture 41: "Case Studies: Intel Montecito and Sun Niagara"
 

Thread urgency

  • Each thread has eight urgency levels
    • Every L3 miss decrements urgency by one
    • Every L3 refill increments urgency by one until urgency reaches 5
    • A switch due to time quantum expiry sets the urgency of the switched thread to 7
    • Arrival of asynchronous interrupt for a background thread sets the urgency level of that thread to 6
    • Switch from L3 miss requires urgency level to be compared also
      Reproduced from IEEE Micro

Core arbiter

Reproduced from IEEE Micro