Virtually indexed caches

• Recall that to have concurrent accesses to TLB and cache, L1 caches are often made virtually indexed
  • Can read the physical tag and data while the TLB lookup takes place
  • Later compare the tag for hit/miss detection
  • How does it impact the functioning of coherence protocols and snoop logic?
• Even for uniprocessor the synonym problem
  • Two different virtual addresses may map to the same physical page frame
  • One simple solution may be to flush all cache lines mapped to a page frame at the time of replacement
  • But this clearly prevents page sharing between two processes

Virtual indexing

• Software normally employs page coloring to solve the synonym issue
  • Allow two virtual pages to point to the same physical page frame only if the two virtual addresses have at least lower k bits common where k is equal to cache line block offset plus log2 (number of cache sets)
  • This guarantees that in a virtually indexed cache, lines from both pages will map to the same index range
• What about the snoop logic?
  • Putting virtual address on the bus requires a VA to PA translation in the snoop so that physical tags can be generated (adds extra latency to snoop and also requires duplicate set of translations)
  • Putting physical address on the bus requires a reverse translation to generate the virtual index (requires an inverted page table)
• Dual tags (Goodman, 1987)
  • Hardware solution to avoid synonyms in shared memory
  • Maintain virtual and physical tags; each corresponding tag pair points to each other
  • Assume no page coloring
  • Use virtual address to look up cache (i.e. virtual index and virtual tag) from processor side; if it hits everything is fine; if it misses use the physical address to look up the physical tag and if it hits follow the physical tag to virtual tag pointer to find the index
  • If virtual tag misses and physical tag hits, that means the synonym problem has happened i.e. two different VAs are mapped to the same PA; in this case invalidate the cache line pointed to by physical tag, replace the line at the virtual index of the current virtual address, place the contents of the invalidated line there and update the physical tag pointer to point to the new virtual index
• Goodman, 1987
  • Always use physical address for snooping
  • Obviates the need for a TLB in memory controller
  • The physical tag is used to look up the cache for snoop decision
  • In case of a snoop hit the pointer stored with the physical tag is followed to get the virtual index and then the cache block can be accessed if needed (e.g., in M state)
  • Note that even if there are two different types of tags the state of a cache line is the same and does not depend on what type of tag is used to access the line
• Multi-level cache hierarchy
  • Normally the L1 cache is designed to be virtually indexed and other levels are physically indexed
  • L2 sends interventions to L1 by communicating the PA
  • L1 must determine the virtual index from that to access the cache: dual tags are sufficient for this purpose