Conflict resolution

• Use the pending request table to resolve conflicts
  • Every processor has a copy of the table
  • Before arbitrating for the address bus every processor looks up the table to see if there is a match
  • In case of a match the request is not issued and is held in a pending buffer
• Flow control is needed at different levels
  • Essentially need to detect if any buffer is full
  • SGI Challenge uses a separate NACK line for each of address and data phases
  • Before the phases reach the “ack” cycle any cache controller can assert the NACK line if it runs out of some critical buffer; this invalidates the transaction and the requester must retry (may use back-off and/or priority)
  • Sun Enterprise requires the receiver to generate the retry when it has buffer space (thus only one retry)

Path of a cache miss

• Assume a read miss
  • Look up request table; in case of a match with BusRd just mark the entry indicating that this processor will snoop the response from the bus and that it will also assert the shared line
  • In case of a request table hit with BusRdX the cache controller must hold on to the request until the conflict resolves
  • In case of a request table miss the requester arbitrates for address bus; while arbitrating if a conflicting request arrives, the controller must put a NOP transaction within the slot it is granted and hold on to the request until the conflict resolves
• Suppose the requester succeeds in putting the request on address/command bus
  • Other cache controllers snoop the request, register it in request table (the requester also does this), take appropriate coherence action within own cache hierarchy, main memory also starts fetching the cache line
  • If a cache holds the line in M state it should source it on bus during response phase; it keeps the inhibit line asserted until it gets the data bus; then it lowers inhibit line and asserts the modified line; at this point the memory controller aborts the data fetch/response and instead fields the line from the data bus for writing back
• If the memory fetches the line even before the snoop is complete, the inhibit line will not allow the memory controller to launch the data on bus
  • After the inhibit line is lowered depending on the state of the modified line memory cancels the data response
  • If no one has the line in M state, the requester grabs the response from memory
• A store miss is similar
  • Only difference is that even if a cache has the line in M state, the memory controller does not write the response back
  • Also any pending BusUpgr to the same cache line must be converted to BusReadX

Write serialization

• In a split-transaction bus setting, the request table provides sufficient support for write serialization
  • Requests to the same cache line are not allowed to proceed at the same time
  • A read to a line after a write to the same line can be launched only after the write response phase has completed; this guarantees that the read will see the new value
  • A write after a read to the same line can be started only after the read response has completed; this guarantees that the value of the read cannot be altered by the value written