Recap of inclusion

• A processor read
  • Looks up L1 first and in case of miss goes to L2, and finally may need to launch a BusRd request if it misses in L2
  • Finally, the line is in S state in both L1 and L2
• A processor write
  • Looks up L1 first and if it is in I state sends a ReadX request to L2 which may have the line in M state
  • In case of L2 hit, the line is filled in M state in L1
  • In case of L2 miss, if the line is in S state in L2 it launches BusUpgr; otherwise it launches BusRdX; finally, the line is in state M in both L1 and L2
  • If the line is in S state in L1, it sends an upgrade request to L2 and either there is an L2 hit or L2 just conveys the upgrade to bus (Why can’t it get changed to BusRdX?)
• L1 cache replacement
  • Replacement of a line in S state may or may not be conveyed to L2
  • Replacement of a line in M state must be sent to L2 so that it can hold the most up-to-date copy
  • The line is in I state in L1 after replacement, the state of line remains unchanged in L2
• L2 cache replacement
  • Replacement of a line in S state may or may not generate a bus transaction; it must send a notification to the L1 caches so that they can invalidate the line to maintain inclusion
  • Replacement of a line in M state first asks the L1 cache to send all the relevant L1 lines (these are the most up-to-date copies) and then launches a BusWB
  • The state of line in both L1 and L2 is I after replacement
• Replacement of a line in E state from L1?
• Replacement of a line in E state from L2?
• Replacement of a line in O state from L1?
• Replacement of a line in O state from L2?
• In summary
  • A line in S state in L2 may or may not be in L1 in S state
  • A line in M state in L2 may or may not be in L1 in M state; Why? Can it be in S state?
  • A line in I state in L2 must not be present in L

Inclusion and snoop

• BusRd snoop
  • Look up L2 cache tag; if in I state no action; if in S state no action; if in M state assert wired-OR M line, send read intervention to L1 data cache, L1 data cache sends lines back, L2 controller launches line on bus, both L1 and L2 lines go to S state
• BusRdX snoop
  • Look up L2 cache tag; if in I state no action; if in S state invalidate and also notify L1; if in M state assert wired-OR M line, send readX intervention to L1 data cache, L1 data cache sends lines back, L2 controller launches line on bus, both L1 and L2 lines go to I state
• BusUpgr snoop
  • Similar to BusRdX without the cache line flush

L2 to L1 interventions

• Two types of interventions
  • One is read/readX intervention that requires data reply
  • Other is plain invalidation that does not need data reply
• Data interventions can be eliminated by making L1 cache write-through
  • But introduces too much of write traffic to L2
  • One possible solution is to have a store buffer that can handle the stores in background obeying the available BW, so that the processor can proceed independently; this can easily violate sequential consistency unless store buffer also becomes a part of snoop logic
• Useless invalidations can be eliminated by introducing an inclusion bit in L2 cache state