Snoop logic

• Couple of decisions need to be taken while designing the snoop logic
  • How long should the snoop decision take?
  • How should processors convey the snoop decision?
• Snoop latency (three design choices)
  • Possible to set an upper bound in terms of number of cycles; advantage: no change in memory controller hardware; disadvantage: potentially large snoop latency (Pentium Pro, Sun Enterprise servers)
  • The memory controller samples the snoop results every cycle until all caches have completed snoop (SGI Challenge uses this approach where the memory controller fetches the line from memory, but stalls if all caches haven’t yet snooped)
  • Maintain a bit per memory line to indicate if it is in M state in some cache
• Conveying snoop result
  • For MESI the bus is augmented with three wired-OR snoop result lines (shared, modified, valid); the valid line is active low
  • The original Illinois MESI protocol requires cache-to-cache transfer even when the line is in S state; this may complicate the hardware enormously due to the involved priority mechanism
  • Commercial MESI protocols normally allow cache-to-cache sharing only for lines in M state
  • SGI Challenge and Sun Enterprise allow cache-to-cache transfers only in M state; Challenge updates memory when going from M to S while Enterprise exercises a MOESI protocol

Writebacks

• Writebacks are essentially eviction of modified lines
  • Caused by a miss mapping to the same cache index
  • Needs two bus transactions: one for the miss and one for the writeback
  • Definitely the miss should be given first priority since this directly impacts forward progress of the program
  • Need a writeback buffer (WBB) to hold the evicted line until the bus can be acquired for the second time by this cache
  • In the meantime a new request from another processor may be launched for the evicted line: the evicting cache must provide the line from the WBB and cancel the pending writeback (need an address comparator with WBB)

A simple design