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Multiprocessors on
A Snoopy Bus
Agenda
Correctness goals
A simple design
Cache controller
Snoop logic
Writebacks
A simple design
Inherently non-atomic
Write serialization
Fetch deadlock
Livelock
Starvation
More on LL/SC
Multi-level caches |
[From Chapter 6 of Culler, Singh, Gupta] |
