RISC processors

• All these atomic instructions deviate from the RISC line
  • Instruction needs a load as well as a store
• Also, it would be great if we can offer a few simple instructions with which we can build most of the atomic primitives
  • Note that it is impossible to build atomic fetch & inc with xchg instruction
• MIPS, Alpha and IBM processors support a pair of instructions: LL and SC
  • Load linked and store conditional

LL/SC

• Load linked behaves just like a normal load with some extra tricks
  • Puts the loaded value in destination register as usual
  • Sets a load_linked bit residing in cache controller to 1
  • Puts the address in a special lock_address register residing in the cache controller
• Store conditional is a special store
  • sc reg, addr stores value in reg to addr only if load_linked bit is set; also it copies the value in load_linked bit to reg and resets load_linked bit
• Any intervening “operation” (e.g., bus transaction or cache replacement) to the cache line containing the address in lock_address register clears the load_linked bit so that subsequent sc fails

Locks with LL/SC

• Test & set

  Lock:  LL r1, lock_addr           /* Normal read miss/BusRead */
            addi r2, r0, 0x1
            SC r2, lock_addr          /* Possibly upgrade miss */
            beqz r2, Lock              /* Check if SC succeeded */
            bnez r1, Lock              /* Check if someone is in CS */

• LL/SC is best-suited for test & test & set locks

  Lock:  LL r1, lock_addr
            bnez r1, Lock
            addi r1, r0, 0x1
            SC r1, lock_addr
            beqz r1, Lock

Fetch & op with LL/SC

• Fetch & inc

  Try:   LL r1, addr
          addi r1, r1, 0x1
          SC r1, addr
          beqz r1, Try

• Compare & swap: Compare with r1, swap r2 and memory location (here we keep on trying until comparison passes)

  Try:  LL r3, addr
         sub r4, r3, r1
         bnez r4, Try
         add r4, r2, r0
         SC r4, addr
         beqz r4, Try
         add r2, r3, r0