Hardwired locks

• Not popular today
  • Less flexible
  • Cannot support large number of locks
• Possible designs
  • Dedicated lock line in bus so that the lock holder keeps it asserted and waiters snoop the lock line in hardware
  • Set of lock registers shared among processors and lock holder gets a lock register (Cray Xmp)

Software locks

• Bakery algorithm
  Shared: choosing[P] = FALSE, ticket[P] = 0;
  Acquire: choosing[i] = TRUE; ticket[i] = max(ticket[0],…,ticket[P-1]) + 1; choosing[i] = FALSE;
    for j = 0 to P-1
    while (choosing[j]);
    while (ticket[j] && ((ticket[j], j) < (ticket[i], i)));
    endfor
  Release: ticket[i] = 0;
• Does it work for multiprocessors?
  • Assume sequential consistency
  • Performance issues related to coherence?
• Too much overhead: need faster and simpler lock algorithms
  • Need some hardware support

Hardware support

• Start with a simple software lock
  Shared: lock = 0;
  Acquire: while (lock); lock = 1;
  Release or Unlock: lock = 0;
• Assembly translation
  Lock: lw register, lock_addr  /* register is any processor register */
         bnez register, Lock
         addi register, register, 0x1
         sw register, lock_addr
  Unlock: xor register, register, register
            sw register, lock_addr
• Does it work?
  • What went wrong?
  • We wanted the read-modify-write sequence to be atomic