Complication with stores

• In OOO execution instructions issue out of program order
  • A store may issue out of program order
  • But it cannot write its value to cache until it retires i.e. comes to the head of ROB; Why? (assume 1p)
  • So its value is kept in a store buffer (this is normally part of the store queue entry occupied by the store)
  • If it hits in the cache (i.e. a write hit), nothing happens
  • If it misses in the cache, either a ReadX or an Upgrade request is issued on the bus depending on the state of the requested cache line
  • Until the store retires subsequent loads from the same processor to the same address can steal the value from store buffer (why not the old value?)

What about others?

• Take the following example (assume invalidation-based protocol)
  • P0 writes x, P1 reads x
  • P0 issues store, assume that it hits in cache, but it commits much later (any simple reason?)
  • P1 issues BusRd (Can it hit in P1’s cache?)
  • Snoop logic in P0’s cache controller finds that it is responsible for sourcing the cache line (M state)
  • What value of x does the launched cache line contain? New value or the old value?
  • After this BusRd what is the state of P0’s line?
  • After this BusRd can the loads from P0 still continue to use the value written by the store?
  • What happens when P0 ultimately commits the store?
• Take the following example (assume invalidation-based protocol)
  • P0 writes x, P1 reads x
  • P0 issues store, assume that it hits in cache, but it commits much later (any simple reason?)
  • P1 issues BusRd (Can it hit in P1’s cache?)
  • Snoop logic in P0’s cache controller finds that it is responsible for sourcing the cache line (M state)
  • What value of x does the launched cache line contain? New value or the old value? OLD VALUE
  • After this BusRd what is the state of P0’s line? S
  • After this BusRd can the matching loads from P0 still continue to use the value written by the store? YES
  • What happens when P0 ultimately commits the store? UPGRADE MISS

More example

• In the previous example same situation may arise even if P0 misses in the cache; the timing of P1’s read decides whether the race happens or not
• Another example
  • P0 writes x, P1 writes x
  • Suppose the race does happen i.e. P1 launches BusRdX before P0’s store commits (Can P1 launch upgrade?)
  • Surely the launched cache line will have old value of x as before
  • Is it safe for the matching loads from P0 to use the new value of x from store buffer?
  • What happens when P0’s store ultimately commits?
• In the previous example same situation may arise even if P0 misses in the cache; the timing of P1’s read decides whether the race happens or not
• Another example
  • P0 writes x, P1 writes x
  • Suppose the race does happen i.e. P1 launches BusRdX before P0’s store commits (Can P1 launch upgrade?)
  • Surely the launched cache line will have old value of x as before
  • Is it safe for the matching loads from P0 to use the new value of x from store buffer? YES
  • What happens when P0 ’s store ultimately commits? READ-EXCLUSIVE MISS

Yet another example

• Another example
  • P0 reads x, P0 writes x, P1 writes x
  • Suppose the race does happen i.e. P1 launches BusRdX before P0’s store commits
  • Surely the launched cache line will have old value of x as before
  • What value does P0’s load commit?