Niagara Floor-plan:

Implications on Software:

• A tall memory hierarchy
  • Each core could run multiple threads
    • Each core in Niagara runs four threads
  • Within core, threads communicate through private cache (fastest)
  • Across cores communication happens through shared L2 or coherence controller (if tiled)
  • Multiple such chips can be connected over a scalable network
    • Adds one more level of memory hierarchy
• A very non-uniform access stack