Module 9: "Introduction to Shared Memory Multiprocessors"
  Lecture 17: "Introduction to Cache Coherence Protocols"
 

State transition

MESI example

  • Take the following example
    • P0 reads x, P0 writes x, P1 reads x, P1 writes x, …

      P0 generates BusRd, memory provides line, P0 puts line in cache in E state

      P0 does write silently, goes to M state

      P1 generates BusRd, P0 provides line, P1 puts line in cache in S state, P0 transitions to S state

      Rest is identical to MSI

    • Consider this example: P0 reads x, P1 reads x, …

      P0 generates BusRd, memory provides line, P0 puts line in cache in E state

      P1 generates BusRd, memory provides line, P1 puts line in cache in S state, P0 transitions to S state (no cache-to-cache sharing)

      Rest is same as MSI