Module 9: "Introduction to Shared Memory Multiprocessors"
  Lecture 17: "Introduction to Cache Coherence Protocols"
 

Invalidation vs. Update

  • Two main classes of protocols:
    • Dictates what action should be taken on a store
    • Invalidation-based protocols invalidate sharers when a store miss appears
    • Update-based protocols update the sharer caches with new value on a store
    • Advantage of update-based protocols: sharers continue to hit in the cache while in invalidation-based protocols sharers will miss next time they try to access the line
    • Advantage of invalidation-based protocols: only store misses go on bus and subsequent stores to the same line are cache hits
  • When is update-based protocol good?
    • What sharing pattern? (large-scale producer/consumer)
    • Otherwise it would just waste bus bandwidth doing useless updates
  • When is invalidation-protocol good?
    • Sequence of multiple writes to a cache line
    • Saves intermediate write transactions
  • Overhead of initiating small updates
    • Invalidation-based protocols are much more popular
    • Some systems support both or maybe some hybrid based on dynamic sharing pattern of a cache line

Sharing patterns

  • Producer-consumer (initially flag, done are zero)
    T0: while (!exit) {x=y; flag=1; while (done != k); flag=0; done=0;}
    T1 to Tk: while (!exit) {while (!flag); use x; done++; while (flag);}
    • Exit condition not shown
    • What if T1 to Tk do not have the outer loop?
  • Migratory (initially flag is zero)
    T0: x = f0(x); flag++;
    T1 to Tk: while (flag != pid); x = f1(x); flag++;
    • Migratory hand-off?

Migratory hand-off

  • Needs a memory writeback on every hand-off
    • r0, w0, r1, w1, r2, w2, r3, w3, r4, w4, …
    • How to avoid these unnecessary writebacks?
    • Saves memory bandwidth
    • Solution: add an owner state (different from M) in caches
    • Only owner can write a line back on eviction
    • Ownership shifts along the migratory chain