In this instruction sequence, consider that is a conditional branch instruction.

The result of the instruction will be available at clock cycle 5. But by that time the fetch unit has already fetched the instruction and

If the branch condition is false, then branch won't take place and the next instruction to be executed is which is already fetched and available for execution.

Now consider that when the condition is true, we have to execute the instruction After clock cycle 5, it is known that branch condition is true and now instruction has to be executed.

But already the processor has fetched instruction and It is required to invalidate these two fetched instruction and the pipe line must be loaded with new destination instruction .

Due to this reason, the pipeline will stall for some time. The time lost due to branch instruction is often referred as branch penalty.