Here register is used as a counter to determine the number of times the contents of register are sifted left.
Consider a processor with a two-stage pipeline and one delay slot. During the execution phase of the instruction , the fetch unit will fetch the instruction After evaluating the branch condition only, it will be clear whether instruction or will be executed next.
The nature of the code segment says that it will remain in the top depending on the initial value of and when it becomes zero, it will come out from the loop and execute the instruction . During the loop execution, every time there is a wrong fetch of instruction . The code segment can be recognized without disturbing the original meaning of the program. The reordered code segment is shown in Figure 9.14.

LOOP	Decrement	R2
	Branch_if 0	LOOP
	Shift_left	R1
NEXT	Add	R1,R3

Figure 9.14: Reordered instructions for program loop