The processing of an instruction need not be divided into only two steps. To gain further speed up, the pipeline must have more stages.

Let us consider the following decomposition of the instruction execution:

• Fetch Instruction (FI): Read the next expected instruction into a buffer.


• Decode Instruction ((DI): Determine the opcode and the operand specifiers.


• Calculate Operand (CO): calculate the effective address of each source operand.


• Fetch Operands(FO): Fetch each operand from memory.


• Execute Instruction (EI): Perform the indicated operation.


• Write Operand(WO): Store the result in memory.

There will be six different stages for these six subtasks. For the sake of simplicity, let us assume the equal duration to perform all the subtasks. It the six stages are not of equal duration, there will be some waiting involved at various pipeline stages.

The timing diagram for the execution of instruction in pipeline fashion is shown in the Figure 9.4.