There are several schemes exist for handling the timing of data transfer over a bus. These can be broadly classified as

• Synchronous bus
  
• Asynchronous bus

Synchronous Bus :

In a synchronous bus, all the devices are synchronised by a common clock, so all devices derive timing information from a common clock line of the bus. A clock pulse on this common clock line defines equal time intervals.

In the simplest form of a synchronous bus, each of these clock pulse constitutes a bus cycle during which one data transfer can take place.

The timing of an input transfer on a synchronous bus is shown in the Figure 7.1.