By looking into the design of the CPU,  we may say that there are various instruction for add operation.  As for example,

	ADD	NUM	R1		Add the contents of memory location specified by NUM to the contents of register R1 .
	ADD	R2	R1		Add the contents of register R2 to the contents of register R1.

The control sequence for execution of these two ADD instructions are different. Of course, the fetch phase of all the instructions remain same.

It is clear that control signals depend on the instruction, i.e., the contents of the instruction register. It is also observed that execution of some of the instructions depend on the contents of condition code or status flag register, where the control sequence depends in conditional branch instruction.