The signal ADD_MD, BR, BRN etc. are coming from instruction decoder circuits which depends on the contents of IR.
The signal T1, T2, T3 etc are coming out from step decoder depends on control step counter.
The signal N (Negative) is coming from condition code register.
When wait for MFC (WMFC) signal is generated, then CPU does not do any works and it waits for an MFC signal from memory unit. In this case, the desired effect is to delay the initiation of the next control step until the MFC signal is received from the main memory. This can be incorporated by inhibiting the advancement of the control step counter for the required period.
Let us assume that the control step counter is controlled by a signal called RUN.
By looking at the control sequence of all the instructions, the WMFC signal is generated as:
WMFC = T2 + T5 . ADD_MD + . . . . . . . . . . . . . .