| Module Name | Download |
|---|---|
| noc20_ee29_assigment_1 | noc20_ee29_assigment_1 |
| noc20_ee29_assigment_2 | noc20_ee29_assigment_2 |
| noc20_ee29_assigment_3 | noc20_ee29_assigment_3 |
| noc20_ee29_assigment_4 | noc20_ee29_assigment_4 |
| noc20_ee29_assigment_5 | noc20_ee29_assigment_5 |
| noc20_ee29_assigment_6 | noc20_ee29_assigment_6 |
| noc20_ee29_assigment_7 | noc20_ee29_assigment_7 |
| noc20_ee29_assigment_8 | noc20_ee29_assigment_8 |
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | MOS Transistor Basics-I | Download |
| 2 | MOS Transistor Basics-II | Download |
| 3 | MOS Transistor Basics-III | Download |
| 4 | MOS Parasitics and SPICE Model | Download |
| 5 | CMOS Inverter Basics-I | Download |
| 6 | CMOS Inverter Basics-II | Download |
| 7 | CMOS Inverter Basics-III | Download |
| 8 | Power Analysis-I | Download |
| 9 | Power Analysis-II | Download |
| 10 | SPICE Simulation-I | Download |
| 11 | SPICE Simulation-II | Download |
| 12 | Combinational Logic Design-I | Download |
| 13 | Combinational Logic Design-II | Download |
| 14 | Combinational Logic Design-III | Download |
| 15 | Combinational Logic Design-IV | Download |
| 16 | Combinational Logic Design-V | Download |
| 17 | Combinational Logic Design-VI | Download |
| 18 | Combinational Logic Design-VII | Download |
| 19 | Combinational Logic Design-VIII | Download |
| 20 | Combinational Logic Design-IX | Download |
| 21 | Combinational Logic Design-X | Download |
| 22 | Logical Efforts-I | Download |
| 23 | Logical Efforts-II | Download |
| 24 | Logical Efforts-III | Download |
| 25 | Sequential Logic Design -I | Download |
| 26 | Sequential Logic Design -II | Download |
| 27 | Sequential Logic Design -III | Download |
| 28 | Sequential Logic Design -IV | Download |
| 29 | Sequential Logic Design -V | Download |
| 30 | Sequential Logic Design -VI | Download |
| 31 | Sequential Logic Design -VII | Download |
| 32 | Sequential Logic Design -VIII | Download |
| 33 | Clocking Strategies for Sequential Design-I | Download |
| 34 | Clocking Strategies for Sequential Design-II | Download |
| 35 | Clocking Strategies for Sequential Design-III | Download |
| 36 | Clocking Strategies for Sequential Design-IV | Download |
| 37 | Sequential Logic Design -IX | Download |
| 38 | Clocking Strategies for Sequential Design-V | Download |
| 39 | Concept of Memory and its Designing-I | Download |
| 40 | Concept of Memory and its Designing-II | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | MOS Transistor Basics-I | Download Verified |
| 2 | MOS Transistor Basics-II | Download Verified |
| 3 | MOS Transistor Basics-III | Download Verified |
| 4 | MOS Parasitics and SPICE Model | Download Verified |
| 5 | CMOS Inverter Basics-I | Download Verified |
| 6 | CMOS Inverter Basics-II | Download To be verified |
| 7 | CMOS Inverter Basics-III | Download To be verified |
| 8 | Power Analysis-I | Download To be verified |
| 9 | Power Analysis-II | Download To be verified |
| 10 | SPICE Simulation-I | Download To be verified |
| 11 | SPICE Simulation-II | Download Verified |
| 12 | Combinational Logic Design-I | Download Verified |
| 13 | Combinational Logic Design-II | Download Verified |
| 14 | Combinational Logic Design-III | Download Verified |
| 15 | Combinational Logic Design-IV | Download Verified |
| 16 | Combinational Logic Design-V | Download To be verified |
| 17 | Combinational Logic Design-VI | Download To be verified |
| 18 | Combinational Logic Design-VII | Download To be verified |
| 19 | Combinational Logic Design-VIII | Download To be verified |
| 20 | Combinational Logic Design-IX | Download To be verified |
| 21 | Combinational Logic Design-X | Download Verified |
| 22 | Logical Efforts-I | Download Verified |
| 23 | Logical Efforts-II | Download Verified |
| 24 | Logical Efforts-III | Download Verified |
| 25 | Sequential Logic Design -I | Download Verified |
| 26 | Sequential Logic Design -II | Download Verified |
| 27 | Sequential Logic Design -III | Download Verified |
| 28 | Sequential Logic Design -IV | Download To be verified |
| 29 | Sequential Logic Design -V | Download To be verified |
| 30 | Sequential Logic Design -VI | Download To be verified |
| 31 | Sequential Logic Design -VII | Download Verified |
| 32 | Sequential Logic Design -VIII | Download Verified |
| 33 | Clocking Strategies for Sequential Design-I | Download Verified |
| 34 | Clocking Strategies for Sequential Design-II | Download Verified |
| 35 | Clocking Strategies for Sequential Design-III | Download Verified |
| 36 | Clocking Strategies for Sequential Design-IV | Download Verified |
| 37 | Sequential Logic Design -IX | Download Verified |
| 38 | Clocking Strategies for Sequential Design-V | Download Verified |
| 39 | Concept of Memory and its Designing-I | Download Verified |
| 40 | Concept of Memory and its Designing-II | Download Verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |