| Module Name | Download | Description | Download Size |
|---|---|---|---|
| Week 1 | noc22-ee55_week1 | ||
| Week 2 | noc22-ee55_week2 | ||
| Week 3 | noc22-ee55_week3 |
| Module Name | Download |
|---|---|
| noc20_ee32_assigment_1 | noc20_ee32_assigment_1 |
| noc20_ee32_assigment_10 | noc20_ee32_assigment_10 |
| noc20_ee32_assigment_11 | noc20_ee32_assigment_11 |
| noc20_ee32_assigment_12 | noc20_ee32_assigment_12 |
| noc20_ee32_assigment_13 | noc20_ee32_assigment_13 |
| noc20_ee32_assigment_2 | noc20_ee32_assigment_2 |
| noc20_ee32_assigment_3 | noc20_ee32_assigment_3 |
| noc20_ee32_assigment_4 | noc20_ee32_assigment_4 |
| noc20_ee32_assigment_5 | noc20_ee32_assigment_5 |
| noc20_ee32_assigment_6 | noc20_ee32_assigment_6 |
| noc20_ee32_assigment_7 | noc20_ee32_assigment_7 |
| noc20_ee32_assigment_8 | noc20_ee32_assigment_8 |
| noc20_ee32_assigment_9 | noc20_ee32_assigment_9 |
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | Lecture 01: Introduction | Download |
| 2 | Lecture 02: Transistor as a switch | Download |
| 3 | Lecture 03: Performance Issues and Introduction to TTL | Download |
| 4 | Lecture 04: Transistor Transistor Logic (TTL) | Download |
| 5 | Lecture 05: CMOS Logic | Download |
| 6 | Lecture 06: Basic Gates and their representations | Download |
| 7 | Lecture 07: Fundamentals of Boolean Algebra | Download |
| 8 | Lecture 08: Boolean Function to Truth Table and Implementaion Issues | Download |
| 9 | Lecture 09: Truth Table to Boolean Function and Implementaion Issues | Download |
| 10 | Lecture 10: Karnugh Map and Digital Circuit Realization | Download |
| 11 | Lecture 11: Karnaugh Map to Entered Variable Map | Download |
| 12 | Lecture 12: Quine - McClusky (QM) Algorithm | Download |
| 13 | Lecture13: Cost Criteria and Minimization of Multiple Output Functions | Download |
| 14 | Lecture 14: Static 1 Hazard | Download |
| 15 | Lecture 15: Static 0 Hazard and Dynamic Hazard | Download |
| 16 | Lecture 16 : Multiplexer: Part I | Download |
| 17 | Lecture 17 : Multiplexer: Part II | Download |
| 18 | Lecture 18 : Demultiplexer / Decoder | Download |
| 19 | Lecture 19 : Decoder with BCD Input and Encoder | Download |
| 20 | Lecture 20 : Parity Generator and Checker | Download |
| 21 | Lecture 21 : Number System | Download |
| 22 | Lecture 22 : Negative Number and 2’s Complement Arithmetic | Download |
| 23 | Lecture 23 : Arithmetic Building Blocks - I | Download |
| 24 | Lecture 24 : Arithmetic Building Blocks - II | Download |
| 25 | Lecture 25 : Overflow Detection and BCD Arithmetic | Download |
| 26 | Lecture 26 : Magnitude Comparator | Download |
| 27 | Lecture 27 : Arithmetic Logic Unit (ALU) | Download |
| 28 | Lecture 28 : Unweighted Code | Download |
| 29 | Lecture 29 : Error Detection and Correction Code | Download |
| 30 | Lecture 30 : Multiplication and Division | Download |
| 31 | Lecture 31: SR Latch and Introduction to Clocked Flip-Flop | Download |
| 32 | Lecture 32: Edge-Triggered Flip-Flop | Download |
| 33 | Lecture 33: Representations of Flip-Flops | Download |
| 34 | Lecture 34: Analysis of Sequential Logic Circuit | Download |
| 35 | Lecture 35: Conversion of Flip-Flops and Flip-Flop Timing Parameters | Download |
| 36 | Lecture 36: Register and Shift Register: PIPO and SISO | Download |
| 37 | Lecture 37: Shift Register: SIPO, PISO and Universal Shift Register | Download |
| 38 | Lecture 38: Application of Shift Register | Download |
| 39 | Lecture 39: Linear Feedback Shift Register | Download |
| 40 | Lecture 40: Serial Addition, Multiplication and Division | Download |
| 41 | Lecture 41: Asynchronous Counter | Download |
| 42 | Lecture 42: Decoding Logic and Synchronous Counter | Download |
| 43 | Lecture 43: Cascading: Mod 2, 3, 5 to Mod 6, 10, 1000 Counter | Download |
| 44 | Lecture 44: Counter Design with Asynchronous Reset and Preset | Download |
| 45 | Lecture 45: Counter Design as Synthesis Problem and Few Other Uses of Counter | Download |
| 46 | Lecture 46 : Synthesis of Sequential Logic Circuit: Moore Model and Mealy Model | Download |
| 47 | Lecture 47 : Moore Model and Mealy Model: Realization of Digital Logic Circuit | Download |
| 48 | Lecture 48 : Algorithmic State Machine (ASM) Chart and Synthesis of Sequential Logic Circuit | Download |
| 49 | Lecture 49 : Circuit Realization from ASM Chart and State Minimization | Download |
| 50 | Lecture 50 : State Minimization by Implication Table and Partitioning Method | Download |
| 51 | Lecture 51 : Digital to Analog Conversion - I | Download |
| 52 | Lecture 52 : Digital to Analog Conversion - II | Download |
| 53 | Lecture 53 : Analog to Digital Conversion - I | Download |
| 54 | Lecture 54 : Analog to Digital Conversion - II | Download |
| 55 | Lecture 55 : Certain Performance Issue of ADC and DAC | Download |
| 56 | Lecture 56: Introduction to Memory | Download |
| 57 | Lecture 57: Static Random Access Memory (SRAM) | Download |
| 58 | Lecture 58: Dynamic RAM(DRAM) and Memory Expansion | Download |
| 59 | Lecture 59: Read Only Memory (ROM) | Download |
| 60 | Lecture 60: PAL, PLA, CPLD, FPGA | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Lecture 01: Introduction | Download Verified |
| 2 | Lecture 02: Transistor as a switch | Download Verified |
| 3 | Lecture 03: Performance Issues and Introduction to TTL | Download Verified |
| 4 | Lecture 04: Transistor Transistor Logic (TTL) | Download Verified |
| 5 | Lecture 05: CMOS Logic | Download Verified |
| 6 | Lecture 06: Basic Gates and their representations | Download Verified |
| 7 | Lecture 07: Fundamentals of Boolean Algebra | Download Verified |
| 8 | Lecture 08: Boolean Function to Truth Table and Implementaion Issues | Download Verified |
| 9 | Lecture 09: Truth Table to Boolean Function and Implementaion Issues | Download Verified |
| 10 | Lecture 10: Karnugh Map and Digital Circuit Realization | Download Verified |
| 11 | Lecture 11: Karnaugh Map to Entered Variable Map | Download Verified |
| 12 | Lecture 12: Quine - McClusky (QM) Algorithm | Download Verified |
| 13 | Lecture13: Cost Criteria and Minimization of Multiple Output Functions | Download Verified |
| 14 | Lecture 14: Static 1 Hazard | Download Verified |
| 15 | Lecture 15: Static 0 Hazard and Dynamic Hazard | Download Verified |
| 16 | Lecture 16 : Multiplexer: Part I | Download Verified |
| 17 | Lecture 17 : Multiplexer: Part II | Download Verified |
| 18 | Lecture 18 : Demultiplexer / Decoder | Download Verified |
| 19 | Lecture 19 : Decoder with BCD Input and Encoder | Download Verified |
| 20 | Lecture 20 : Parity Generator and Checker | Download Verified |
| 21 | Lecture 21 : Number System | Download Verified |
| 22 | Lecture 22 : Negative Number and 2’s Complement Arithmetic | Download Verified |
| 23 | Lecture 23 : Arithmetic Building Blocks - I | Download Verified |
| 24 | Lecture 24 : Arithmetic Building Blocks - II | Download Verified |
| 25 | Lecture 25 : Overflow Detection and BCD Arithmetic | Download Verified |
| 26 | Lecture 26 : Magnitude Comparator | Download Verified |
| 27 | Lecture 27 : Arithmetic Logic Unit (ALU) | Download Verified |
| 28 | Lecture 28 : Unweighted Code | Download Verified |
| 29 | Lecture 29 : Error Detection and Correction Code | Download Verified |
| 30 | Lecture 30 : Multiplication and Division | Download Verified |
| 31 | Lecture 31: SR Latch and Introduction to Clocked Flip-Flop | Download Verified |
| 32 | Lecture 32: Edge-Triggered Flip-Flop | Download Verified |
| 33 | Lecture 33: Representations of Flip-Flops | Download Verified |
| 34 | Lecture 34: Analysis of Sequential Logic Circuit | Download Verified |
| 35 | Lecture 35: Conversion of Flip-Flops and Flip-Flop Timing Parameters | Download Verified |
| 36 | Lecture 36: Register and Shift Register: PIPO and SISO | Download Verified |
| 37 | Lecture 37: Shift Register: SIPO, PISO and Universal Shift Register | Download Verified |
| 38 | Lecture 38: Application of Shift Register | Download Verified |
| 39 | Lecture 39: Linear Feedback Shift Register | Download Verified |
| 40 | Lecture 40: Serial Addition, Multiplication and Division | Download Verified |
| 41 | Lecture 41: Asynchronous Counter | Download Verified |
| 42 | Lecture 42: Decoding Logic and Synchronous Counter | Download Verified |
| 43 | Lecture 43: Cascading: Mod 2, 3, 5 to Mod 6, 10, 1000 Counter | Download Verified |
| 44 | Lecture 44: Counter Design with Asynchronous Reset and Preset | Download Verified |
| 45 | Lecture 45: Counter Design as Synthesis Problem and Few Other Uses of Counter | Download Verified |
| 46 | Lecture 46 : Synthesis of Sequential Logic Circuit: Moore Model and Mealy Model | Download Verified |
| 47 | Lecture 47 : Moore Model and Mealy Model: Realization of Digital Logic Circuit | Download Verified |
| 48 | Lecture 48 : Algorithmic State Machine (ASM) Chart and Synthesis of Sequential Logic Circuit | Download Verified |
| 49 | Lecture 49 : Circuit Realization from ASM Chart and State Minimization | Download Verified |
| 50 | Lecture 50 : State Minimization by Implication Table and Partitioning Method | Download Verified |
| 51 | Lecture 51 : Digital to Analog Conversion - I | Download Verified |
| 52 | Lecture 52 : Digital to Analog Conversion - II | Download Verified |
| 53 | Lecture 53 : Analog to Digital Conversion - I | Download Verified |
| 54 | Lecture 54 : Analog to Digital Conversion - II | Download Verified |
| 55 | Lecture 55 : Certain Performance Issue of ADC and DAC | Download Verified |
| 56 | Lecture 56: Introduction to Memory | Download Verified |
| 57 | Lecture 57: Static Random Access Memory (SRAM) | Download Verified |
| 58 | Lecture 58: Dynamic RAM(DRAM) and Memory Expansion | Download Verified |
| 59 | Lecture 59: Read Only Memory (ROM) | Download Verified |
| 60 | Lecture 60: PAL, PLA, CPLD, FPGA | Download Verified |
| Sl.No | Chapter Name | Hindi |
|---|---|---|
| 1 | Lecture 01: Introduction | Download |
| 2 | Lecture 02: Transistor as a switch | Download |
| 3 | Lecture 03: Performance Issues and Introduction to TTL | Download |
| 4 | Lecture 04: Transistor Transistor Logic (TTL) | Download |
| 5 | Lecture 05: CMOS Logic | Download |
| 6 | Lecture 06: Basic Gates and their representations | Download |
| 7 | Lecture 07: Fundamentals of Boolean Algebra | Download |
| 8 | Lecture 08: Boolean Function to Truth Table and Implementaion Issues | Download |
| 9 | Lecture 09: Truth Table to Boolean Function and Implementaion Issues | Download |
| 10 | Lecture 10: Karnugh Map and Digital Circuit Realization | Download |
| 11 | Lecture 11: Karnaugh Map to Entered Variable Map | Download |
| 12 | Lecture 12: Quine - McClusky (QM) Algorithm | Download |
| 13 | Lecture13: Cost Criteria and Minimization of Multiple Output Functions | Download |
| 14 | Lecture 14: Static 1 Hazard | Download |
| 15 | Lecture 15: Static 0 Hazard and Dynamic Hazard | Download |
| 16 | Lecture 16 : Multiplexer: Part I | Download |
| 17 | Lecture 17 : Multiplexer: Part II | Download |
| 18 | Lecture 18 : Demultiplexer / Decoder | Download |
| 19 | Lecture 19 : Decoder with BCD Input and Encoder | Download |
| 20 | Lecture 20 : Parity Generator and Checker | Download |
| 21 | Lecture 21 : Number System | Download |
| 22 | Lecture 22 : Negative Number and 2’s Complement Arithmetic | Download |
| 23 | Lecture 23 : Arithmetic Building Blocks - I | Download |
| 24 | Lecture 24 : Arithmetic Building Blocks - II | Download |
| 25 | Lecture 25 : Overflow Detection and BCD Arithmetic | Download |
| 26 | Lecture 26 : Magnitude Comparator | Download |
| 27 | Lecture 27 : Arithmetic Logic Unit (ALU) | Download |
| 28 | Lecture 28 : Unweighted Code | Download |
| 29 | Lecture 29 : Error Detection and Correction Code | Download |
| 30 | Lecture 30 : Multiplication and Division | Download |
| 31 | Lecture 31: SR Latch and Introduction to Clocked Flip-Flop | Download |
| 32 | Lecture 32: Edge-Triggered Flip-Flop | Download |
| 33 | Lecture 33: Representations of Flip-Flops | Download |
| 34 | Lecture 34: Analysis of Sequential Logic Circuit | Download |
| 35 | Lecture 35: Conversion of Flip-Flops and Flip-Flop Timing Parameters | Download |
| 36 | Lecture 36: Register and Shift Register: PIPO and SISO | Download |
| 37 | Lecture 37: Shift Register: SIPO, PISO and Universal Shift Register | Download |
| 38 | Lecture 38: Application of Shift Register | Download |
| 39 | Lecture 39: Linear Feedback Shift Register | Download |
| 40 | Lecture 40: Serial Addition, Multiplication and Division | Download |
| 41 | Lecture 41: Asynchronous Counter | Download |
| 42 | Lecture 42: Decoding Logic and Synchronous Counter | Download |
| 43 | Lecture 43: Cascading: Mod 2, 3, 5 to Mod 6, 10, 1000 Counter | Download |
| 44 | Lecture 44: Counter Design with Asynchronous Reset and Preset | Download |
| 45 | Lecture 45: Counter Design as Synthesis Problem and Few Other Uses of Counter | Download |
| 46 | Lecture 46 : Synthesis of Sequential Logic Circuit: Moore Model and Mealy Model | Download |
| 47 | Lecture 47 : Moore Model and Mealy Model: Realization of Digital Logic Circuit | Download |
| 48 | Lecture 48 : Algorithmic State Machine (ASM) Chart and Synthesis of Sequential Logic Circuit | Download |
| 49 | Lecture 49 : Circuit Realization from ASM Chart and State Minimization | Download |
| 50 | Lecture 50 : State Minimization by Implication Table and Partitioning Method | Download |
| 51 | Lecture 51 : Digital to Analog Conversion - I | Download |
| 52 | Lecture 52 : Digital to Analog Conversion - II | Download |
| 53 | Lecture 53 : Analog to Digital Conversion - I | Download |
| 54 | Lecture 54 : Analog to Digital Conversion - II | Download |
| 55 | Lecture 55 : Certain Performance Issue of ADC and DAC | Download |
| 56 | Lecture 56: Introduction to Memory | Download |
| 57 | Lecture 57: Static Random Access Memory (SRAM) | Download |
| 58 | Lecture 58: Dynamic RAM(DRAM) and Memory Expansion | Download |
| 59 | Lecture 59: Read Only Memory (ROM) | Download |
| 60 | Lecture 60: PAL, PLA, CPLD, FPGA | Download |
| Sl.No | Chapter Name | Marathi |
|---|---|---|
| 1 | Lecture 01: Introduction | Download |
| 2 | Lecture 02: Transistor as a switch | Download |
| 3 | Lecture 03: Performance Issues and Introduction to TTL | Download |
| 4 | Lecture 04: Transistor Transistor Logic (TTL) | Download |
| 5 | Lecture 05: CMOS Logic | Download |
| 6 | Lecture 06: Basic Gates and their representations | Download |
| 7 | Lecture 07: Fundamentals of Boolean Algebra | Download |
| 8 | Lecture 08: Boolean Function to Truth Table and Implementaion Issues | Download |
| 9 | Lecture 09: Truth Table to Boolean Function and Implementaion Issues | Download |
| 10 | Lecture 10: Karnugh Map and Digital Circuit Realization | Download |
| 11 | Lecture 11: Karnaugh Map to Entered Variable Map | Download |
| 12 | Lecture 12: Quine - McClusky (QM) Algorithm | Download |
| 13 | Lecture13: Cost Criteria and Minimization of Multiple Output Functions | Download |
| 14 | Lecture 14: Static 1 Hazard | Download |
| 15 | Lecture 15: Static 0 Hazard and Dynamic Hazard | Download |
| 16 | Lecture 16 : Multiplexer: Part I | Download |
| 17 | Lecture 17 : Multiplexer: Part II | Download |
| 18 | Lecture 18 : Demultiplexer / Decoder | Download |
| 19 | Lecture 19 : Decoder with BCD Input and Encoder | Download |
| 20 | Lecture 20 : Parity Generator and Checker | Download |
| 21 | Lecture 21 : Number System | Download |
| 22 | Lecture 22 : Negative Number and 2’s Complement Arithmetic | Download |
| 23 | Lecture 23 : Arithmetic Building Blocks - I | Download |
| 24 | Lecture 24 : Arithmetic Building Blocks - II | Download |
| 25 | Lecture 25 : Overflow Detection and BCD Arithmetic | Download |
| 26 | Lecture 26 : Magnitude Comparator | Download |
| 27 | Lecture 27 : Arithmetic Logic Unit (ALU) | Download |
| 28 | Lecture 28 : Unweighted Code | Download |
| 29 | Lecture 29 : Error Detection and Correction Code | Download |
| 30 | Lecture 30 : Multiplication and Division | Download |
| 31 | Lecture 31: SR Latch and Introduction to Clocked Flip-Flop | Download |
| 32 | Lecture 32: Edge-Triggered Flip-Flop | Download |
| 33 | Lecture 33: Representations of Flip-Flops | Download |
| 34 | Lecture 34: Analysis of Sequential Logic Circuit | Download |
| 35 | Lecture 35: Conversion of Flip-Flops and Flip-Flop Timing Parameters | Download |
| 36 | Lecture 36: Register and Shift Register: PIPO and SISO | Download |
| 37 | Lecture 37: Shift Register: SIPO, PISO and Universal Shift Register | Download |
| 38 | Lecture 38: Application of Shift Register | Download |
| 39 | Lecture 39: Linear Feedback Shift Register | Download |
| 40 | Lecture 40: Serial Addition, Multiplication and Division | Download |
| 41 | Lecture 41: Asynchronous Counter | Download |
| 42 | Lecture 42: Decoding Logic and Synchronous Counter | Download |
| 43 | Lecture 43: Cascading: Mod 2, 3, 5 to Mod 6, 10, 1000 Counter | Download |
| 44 | Lecture 44: Counter Design with Asynchronous Reset and Preset | Download |
| 45 | Lecture 45: Counter Design as Synthesis Problem and Few Other Uses of Counter | Download |
| 46 | Lecture 46 : Synthesis of Sequential Logic Circuit: Moore Model and Mealy Model | Download |
| 47 | Lecture 47 : Moore Model and Mealy Model: Realization of Digital Logic Circuit | Download |
| 48 | Lecture 48 : Algorithmic State Machine (ASM) Chart and Synthesis of Sequential Logic Circuit | Download |
| 49 | Lecture 49 : Circuit Realization from ASM Chart and State Minimization | Download |
| 50 | Lecture 50 : State Minimization by Implication Table and Partitioning Method | Download |
| 51 | Lecture 51 : Digital to Analog Conversion - I | Download |
| 52 | Lecture 52 : Digital to Analog Conversion - II | Download |
| 53 | Lecture 53 : Analog to Digital Conversion - I | Download |
| 54 | Lecture 54 : Analog to Digital Conversion - II | Download |
| 55 | Lecture 55 : Certain Performance Issue of ADC and DAC | Download |
| 56 | Lecture 56: Introduction to Memory | Download |
| 57 | Lecture 57: Static Random Access Memory (SRAM) | Download |
| 58 | Lecture 58: Dynamic RAM(DRAM) and Memory Expansion | Download |
| 59 | Lecture 59: Read Only Memory (ROM) | Download |
| 60 | Lecture 60: PAL, PLA, CPLD, FPGA | Download |
| Sl.No | Chapter Name | Tamil |
|---|---|---|
| 1 | Lecture 01: Introduction | Download |
| 2 | Lecture 02: Transistor as a switch | Download |
| 3 | Lecture 03: Performance Issues and Introduction to TTL | Download |
| 4 | Lecture 04: Transistor Transistor Logic (TTL) | Download |
| 5 | Lecture 05: CMOS Logic | Download |
| 6 | Lecture 06: Basic Gates and their representations | Download |
| 7 | Lecture 07: Fundamentals of Boolean Algebra | Download |
| 8 | Lecture 08: Boolean Function to Truth Table and Implementaion Issues | Download |
| 9 | Lecture 09: Truth Table to Boolean Function and Implementaion Issues | Download |
| 10 | Lecture 10: Karnugh Map and Digital Circuit Realization | Download |
| 11 | Lecture 11: Karnaugh Map to Entered Variable Map | Download |
| 12 | Lecture 12: Quine - McClusky (QM) Algorithm | Download |
| 13 | Lecture13: Cost Criteria and Minimization of Multiple Output Functions | Download |
| 14 | Lecture 14: Static 1 Hazard | Download |
| 15 | Lecture 15: Static 0 Hazard and Dynamic Hazard | Download |
| 16 | Lecture 16 : Multiplexer: Part I | Download |
| 17 | Lecture 17 : Multiplexer: Part II | Download |
| 18 | Lecture 18 : Demultiplexer / Decoder | Download |
| 19 | Lecture 19 : Decoder with BCD Input and Encoder | Download |
| 20 | Lecture 20 : Parity Generator and Checker | Download |
| 21 | Lecture 21 : Number System | Download |
| 22 | Lecture 22 : Negative Number and 2’s Complement Arithmetic | Download |
| 23 | Lecture 23 : Arithmetic Building Blocks - I | Download |
| 24 | Lecture 24 : Arithmetic Building Blocks - II | Download |
| 25 | Lecture 25 : Overflow Detection and BCD Arithmetic | Download |
| 26 | Lecture 26 : Magnitude Comparator | Download |
| 27 | Lecture 27 : Arithmetic Logic Unit (ALU) | Download |
| 28 | Lecture 28 : Unweighted Code | Download |
| 29 | Lecture 29 : Error Detection and Correction Code | Download |
| 30 | Lecture 30 : Multiplication and Division | Download |
| 31 | Lecture 31: SR Latch and Introduction to Clocked Flip-Flop | Download |
| 32 | Lecture 32: Edge-Triggered Flip-Flop | Download |
| 33 | Lecture 33: Representations of Flip-Flops | Download |
| 34 | Lecture 34: Analysis of Sequential Logic Circuit | Download |
| 35 | Lecture 35: Conversion of Flip-Flops and Flip-Flop Timing Parameters | Download |
| 36 | Lecture 36: Register and Shift Register: PIPO and SISO | Download |
| 37 | Lecture 37: Shift Register: SIPO, PISO and Universal Shift Register | Download |
| 38 | Lecture 38: Application of Shift Register | Download |
| 39 | Lecture 39: Linear Feedback Shift Register | Download |
| 40 | Lecture 40: Serial Addition, Multiplication and Division | Download |
| 41 | Lecture 41: Asynchronous Counter | Download |
| 42 | Lecture 42: Decoding Logic and Synchronous Counter | Download |
| 43 | Lecture 43: Cascading: Mod 2, 3, 5 to Mod 6, 10, 1000 Counter | Download |
| 44 | Lecture 44: Counter Design with Asynchronous Reset and Preset | Download |
| 45 | Lecture 45: Counter Design as Synthesis Problem and Few Other Uses of Counter | Download |
| 46 | Lecture 46 : Synthesis of Sequential Logic Circuit: Moore Model and Mealy Model | Download |
| 47 | Lecture 47 : Moore Model and Mealy Model: Realization of Digital Logic Circuit | Download |
| 48 | Lecture 48 : Algorithmic State Machine (ASM) Chart and Synthesis of Sequential Logic Circuit | Download |
| 49 | Lecture 49 : Circuit Realization from ASM Chart and State Minimization | Download |
| 50 | Lecture 50 : State Minimization by Implication Table and Partitioning Method | Download |
| 51 | Lecture 51 : Digital to Analog Conversion - I | Download |
| 52 | Lecture 52 : Digital to Analog Conversion - II | Download |
| 53 | Lecture 53 : Analog to Digital Conversion - I | Download |
| 54 | Lecture 54 : Analog to Digital Conversion - II | Download |
| 55 | Lecture 55 : Certain Performance Issue of ADC and DAC | Download |
| 56 | Lecture 56: Introduction to Memory | Download |
| 57 | Lecture 57: Static Random Access Memory (SRAM) | Download |
| 58 | Lecture 58: Dynamic RAM(DRAM) and Memory Expansion | Download |
| 59 | Lecture 59: Read Only Memory (ROM) | Download |
| 60 | Lecture 60: PAL, PLA, CPLD, FPGA | Download |