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Sl.No Chapter Name English
1Introduction to Digital VLSI Design FlowDownload
To be verified
2High-level Synthesis (HLS) flow with an exampleDownload
To be verified
3Automation of High-level Synthesis Steps Download
To be verified
4Impact of Coding Style on HLS Results Download
To be verified
5Impact of Compiler Optimizations on HLS ResultsDownload
To be verified
6RTL Optimizations for TimingDownload
To be verified
7RetimingDownload
To be verified
8RTL Optimizations for AreaDownload
To be verified
9RTL Optimizations for PowerDownload
To be verified
10High Level Synthesis: Introduction to Logic SynthesisDownload
To be verified
11Overview of FPGA Technology MappingDownload
To be verified
12 Introduction to Physical SynthesisDownload
To be verified
13Introduction to Digital VLSI Testing-IDownload
To be verified
14Introduction to Digital VLSI Testing-IIDownload
To be verified
15Optimization Techniques for ATPGDownload
To be verified
16Optimization Techniques for ATPG [Part II]Download
To be verified
17Optimization Techniques for Design for TestabilityDownload
To be verified
18High-level fault modeling and RTL level TestingDownload
To be verified
19LTL/CTL based VerificationDownload
To be verified
20Verification of Large Scale SystemsDownload
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21BDD based verificationDownload
To be verified
22Verification: ADD based verification, HDD based verificationDownload
To be verified
23Verification: Symbolic Model CheckingDownload
To be verified
24Verification: Bounded Model CheckingDownload
To be verified


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1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
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