Sl.No | Chapter Name | English |
---|---|---|
1 | Introduction to Digital VLSI Design Flow | Download To be verified |
2 | High-level Synthesis (HLS) flow with an example | Download To be verified |
3 | Automation of High-level Synthesis Steps | Download To be verified |
4 | Impact of Coding Style on HLS Results | Download To be verified |
5 | Impact of Compiler Optimizations on HLS Results | Download To be verified |
6 | RTL Optimizations for Timing | Download To be verified |
7 | Retiming | Download To be verified |
8 | RTL Optimizations for Area | Download To be verified |
9 | RTL Optimizations for Power | Download To be verified |
10 | High Level Synthesis: Introduction to Logic Synthesis | Download To be verified |
11 | Overview of FPGA Technology Mapping | Download To be verified |
12 | Introduction to Physical Synthesis | Download To be verified |
13 | Introduction to Digital VLSI Testing-I | Download To be verified |
14 | Introduction to Digital VLSI Testing-II | Download To be verified |
15 | Optimization Techniques for ATPG | Download To be verified |
16 | Optimization Techniques for ATPG [Part II] | Download To be verified |
17 | Optimization Techniques for Design for Testability | Download To be verified |
18 | High-level fault modeling and RTL level Testing | Download To be verified |
19 | LTL/CTL based Verification | Download To be verified |
20 | Verification of Large Scale Systems | Download To be verified |
21 | BDD based verification | Download To be verified |
22 | Verification: ADD based verification, HDD based verification | Download To be verified |
23 | Verification: Symbolic Model Checking | Download To be verified |
24 | Verification: Bounded Model Checking | Download To be verified |
Sl.No | Language | Book link |
---|---|---|
1 | English | Not Available |
2 | Bengali | Not Available |
3 | Gujarati | Not Available |
4 | Hindi | Not Available |
5 | Kannada | Not Available |
6 | Malayalam | Not Available |
7 | Marathi | Not Available |
8 | Tamil | Not Available |
9 | Telugu | Not Available |