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Electrical Engineering
NOC:Optimization Techniques for Digital VLSI Design (Video)
Syllabus
Co-ordinated by :
IIT Guwahati
Available from :
2017-12-22
Lec :
1
Modules / Lectures
Introduction and High-level Synthesis
Introduction to Digital VLSI Design Flow
High-level Synthesis (HLS) flow with an example
Automation of High-level Synthesis Steps
Optimizations for HLS and RTL Optimizations
Impact of Coding Style on HLS Results
Impact of Compiler Optimizations on HLS Results
RTL Optimizations for Timing
RTL Optimizations
Retiming
RTL Optimizations for Area
RTL Optimizations for Power
Logic Synthesis and Physical Synthesis
High Level Synthesis: Introduction to Logic Synthesis
Overview of FPGA Technology Mapping
Introduction to Physical Synthesis
VLSI Testing 1
Introduction to Digital VLSI Testing-I
Introduction to Digital VLSI Testing-II
Optimization Techniques for ATPG
VLSI Testing 2
Optimization Techniques for ATPG [Part II]
Optimization Techniques for Design for Testability
High-level fault modeling and RTL level Testing
Verification 1
LTL/CTL based Verification
Verification of Large Scale Systems
BDD based verification
Verification 2
Verification: ADD based verification, HDD based verification
Verification: Symbolic Model Checking
Verification: Bounded Model Checking
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Chapter Name
English
1
Introduction to Digital VLSI Design Flow
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2
High-level Synthesis (HLS) flow with an example
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3
Automation of High-level Synthesis Steps
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4
Impact of Coding Style on HLS Results
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5
Impact of Compiler Optimizations on HLS Results
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6
RTL Optimizations for Timing
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7
Retiming
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8
RTL Optimizations for Area
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9
RTL Optimizations for Power
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10
High Level Synthesis: Introduction to Logic Synthesis
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