| Name | Download | Download Size |
|---|---|---|
| Lecture Note | Download as zip file | 23M |
| Module Name | Download |
|---|---|
| noc19_cs74_assessment_id_Week_1 | noc19_cs74_assessment_id_Week_1 |
| noc19_cs74_assessment_id_Week_10 | noc19_cs74_assessment_id_Week_10 |
| noc19_cs74_assessment_id_Week_11 | noc19_cs74_assessment_id_Week_11 |
| noc19_cs74_assessment_id_Week_12 | noc19_cs74_assessment_id_Week_12 |
| noc19_cs74_assessment_id_Week_2 | noc19_cs74_assessment_id_Week_2 |
| noc19_cs74_assessment_id_Week_3 | noc19_cs74_assessment_id_Week_3 |
| noc19_cs74_assessment_id_Week_4 | noc19_cs74_assessment_id_Week_4 |
| noc19_cs74_assessment_id_Week_5 | noc19_cs74_assessment_id_Week_5 |
| noc19_cs74_assessment_id_Week_6 | noc19_cs74_assessment_id_Week_6 |
| noc19_cs74_assessment_id_Week_7 | noc19_cs74_assessment_id_Week_7 |
| noc19_cs74_assessment_id_Week_8 | noc19_cs74_assessment_id_Week_8 |
| noc19_cs74_assessment_id_Week_9 | noc19_cs74_assessment_id_Week_9 |
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | Lecture 01: Introduction | Download |
| 2 | Lecture 02: Octal and Hexadecimal Number Systems | Download |
| 3 | Lecture 03: Signed and Unsigned Binary Number Representation | Download |
| 4 | Lecture 04: Binary Addition and Subtraction | Download |
| 5 | Lecture 05: BCD and Gray Code Representations | Download |
| 6 | Lecture 06: Error Detection and Correction | Download |
| 7 | Lecture 07: Logic Gates | Download |
| 8 | Lecture 08: Logic Families to Implement Gates | Download |
| 9 | Lecture 09: Emerging Technologies (Part I) | Download |
| 10 | Lecture 10: Emerging Technologies (Part II) | Download |
| 11 | Lecture 11 : Switching Algebra | Download |
| 12 | Lecture 12 : Algebraic Manipulation | Download |
| 13 | Lecture 13 : Properties of Switching Functions | Download |
| 14 | Lecture 14 : Obtaining Canonical Representations of Functions | Download |
| 15 | Lecture 15 : Functional Completeness | Download |
| 16 | Lecture 16: Minimization Using Karnaugh Maps (Part I) | Download |
| 17 | Lecture 17: Minimization Using Karnaugh Maps (Part II) | Download |
| 18 | Lecture 21: Design of Adders (Part I) | Download |
| 19 | Lecture 22: Design of Adders (Part II) | Download |
| 20 | Lecture 23: Design of Adders (Part III) | Download |
| 21 | Lecture 24: Logic Design(Part I) | Download |
| 22 | Lecture 25: Logic Design(Part II) | Download |
| 23 | Lecture 26: Logic Design(Part III) | Download |
| 24 | Lecture 27: Binary Decision Diagrams (Part I) | Download |
| 25 | Lecture 28: Binary Decision Diagrams (Part II) | Download |
| 26 | Lecture 29: Logic Design using AND-EXOR Network | Download |
| 27 | Lecture 30: Threshold Logic and Threshold Gates | Download |
| 28 | Lecture 31: Latches and Flip-Flops (Part I) | Download |
| 29 | Lecture 32: Latches and Flip-Flops (Part II) | Download |
| 30 | Lecture 33: Latches and Flip-Flops (Part III) | Download |
| 31 | Lecture 34: Clocking and Timing (Part I) | Download |
| 32 | Lecture 35: Clocking and Timing (Part II) | Download |
| 33 | Lecture 36: Synthesis of Synchronous Sequential Circuits (Part I) | Download |
| 34 | Lecture 37: Synthesis of Synchronous Sequential Circuits (Part II) | Download |
| 35 | Lecture 38: Synthesis of Synchronous Sequential Circuits (Part III) | Download |
| 36 | Lecture 39: Synthesis of Synchronous Sequential Circuits (Part IV) | Download |
| 37 | Lecture 40: Minimization of Finite State Machines (Part I) | Download |
| 38 | Lecture 41: Minimization of Finite State Machines (Part II) | Download |
| 39 | Lecture 42: Design of Registers (Part I) | Download |
| 40 | Lecture 43: Design of Registers (Part II) | Download |
| 41 | Lecture 44: Design of Registers (Part III) | Download |
| 42 | Lecture 45: Design of Counters (Part I) | Download |
| 43 | Lecture 46: Design of Counters (Part II) | Download |
| 44 | Lecture 47: Digital-to-Analog Converter (Part I) | Download |
| 45 | Lecture 48: Digital-to-Analog Converter (Part II) | Download |
| 46 | Lecture 49: Analog-to-Digital Converter (Part I) | Download |
| 47 | Lecture 50: Analog-to-Digital Converter (Part II) | Download |
| 48 | Lecture 51: Analog-to-Digital Converter (Part III) | Download |
| 49 | Lecture 52: Asynchronous Sequential Circuits (Part I) | Download |
| 50 | Lecture 53: Asynchronous Sequential Circuits (Part II) | Download |
| 51 | Lecture 54: Algorithmic State Machine (ASM) Chart | Download |
| 52 | Lecture 55 : Testing of Digital Circuits | Download |
| 53 | Lecture 56 : Fault Modeling | Download |
| 54 | Lecture 57 : Test Pattern Generation | Download |
| 55 | Lecture 58 : Design for Testability | Download |
| 56 | Lecture 59 : Built-in Self-Test (Part I) | Download |
| 57 | Lecture 60 : Built-in Self-Test (Part II) | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Lecture 01: Introduction | Download Verified |
| 2 | Lecture 02: Octal and Hexadecimal Number Systems | Download Verified |
| 3 | Lecture 03: Signed and Unsigned Binary Number Representation | Download Verified |
| 4 | Lecture 04: Binary Addition and Subtraction | Download Verified |
| 5 | Lecture 05: BCD and Gray Code Representations | Download Verified |
| 6 | Lecture 06: Error Detection and Correction | Download Verified |
| 7 | Lecture 07: Logic Gates | Download Verified |
| 8 | Lecture 08: Logic Families to Implement Gates | Download Verified |
| 9 | Lecture 09: Emerging Technologies (Part I) | Download Verified |
| 10 | Lecture 10: Emerging Technologies (Part II) | Download Verified |
| 11 | Lecture 11 : Switching Algebra | Download Verified |
| 12 | Lecture 12 : Algebraic Manipulation | Download Verified |
| 13 | Lecture 13 : Properties of Switching Functions | Download Verified |
| 14 | Lecture 14 : Obtaining Canonical Representations of Functions | Download Verified |
| 15 | Lecture 15 : Functional Completeness | Download Verified |
| 16 | Lecture 16: Minimization Using Karnaugh Maps (Part I) | Download Verified |
| 17 | Lecture 17: Minimization Using Karnaugh Maps (Part II) | Download Verified |
| 18 | Lecture 21: Design of Adders (Part I) | Download Verified |
| 19 | Lecture 22: Design of Adders (Part II) | Download Verified |
| 20 | Lecture 23: Design of Adders (Part III) | Download Verified |
| 21 | Lecture 24: Logic Design(Part I) | Download Verified |
| 22 | Lecture 25: Logic Design(Part II) | Download Verified |
| 23 | Lecture 26: Logic Design(Part III) | Download Verified |
| 24 | Lecture 27: Binary Decision Diagrams (Part I) | Download Verified |
| 25 | Lecture 28: Binary Decision Diagrams (Part II) | Download Verified |
| 26 | Lecture 29: Logic Design using AND-EXOR Network | Download Verified |
| 27 | Lecture 30: Threshold Logic and Threshold Gates | Download Verified |
| 28 | Lecture 31: Latches and Flip-Flops (Part I) | Download Verified |
| 29 | Lecture 32: Latches and Flip-Flops (Part II) | Download Verified |
| 30 | Lecture 33: Latches and Flip-Flops (Part III) | Download Verified |
| 31 | Lecture 34: Clocking and Timing (Part I) | Download Verified |
| 32 | Lecture 35: Clocking and Timing (Part II) | Download Verified |
| 33 | Lecture 36: Synthesis of Synchronous Sequential Circuits (Part I) | Download Verified |
| 34 | Lecture 37: Synthesis of Synchronous Sequential Circuits (Part II) | Download Verified |
| 35 | Lecture 38: Synthesis of Synchronous Sequential Circuits (Part III) | Download Verified |
| 36 | Lecture 39: Synthesis of Synchronous Sequential Circuits (Part IV) | Download Verified |
| 37 | Lecture 40: Minimization of Finite State Machines (Part I) | Download Verified |
| 38 | Lecture 41: Minimization of Finite State Machines (Part II) | Download Verified |
| 39 | Lecture 42: Design of Registers (Part I) | Download Verified |
| 40 | Lecture 43: Design of Registers (Part II) | Download Verified |
| 41 | Lecture 44: Design of Registers (Part III) | Download Verified |
| 42 | Lecture 45: Design of Counters (Part I) | Download Verified |
| 43 | Lecture 46: Design of Counters (Part II) | Download Verified |
| 44 | Lecture 47: Digital-to-Analog Converter (Part I) | Download Verified |
| 45 | Lecture 48: Digital-to-Analog Converter (Part II) | Download Verified |
| 46 | Lecture 49: Analog-to-Digital Converter (Part I) | Download Verified |
| 47 | Lecture 50: Analog-to-Digital Converter (Part II) | Download Verified |
| 48 | Lecture 51: Analog-to-Digital Converter (Part III) | Download Verified |
| 49 | Lecture 52: Asynchronous Sequential Circuits (Part I) | Download Verified |
| 50 | Lecture 53: Asynchronous Sequential Circuits (Part II) | Download Verified |
| 51 | Lecture 54: Algorithmic State Machine (ASM) Chart | Download Verified |
| 52 | Lecture 55 : Testing of Digital Circuits | Download Verified |
| 53 | Lecture 56 : Fault Modeling | Download Verified |
| 54 | Lecture 57 : Test Pattern Generation | Download Verified |
| 55 | Lecture 58 : Design for Testability | Download Verified |
| 56 | Lecture 59 : Built-in Self-Test (Part I) | Download Verified |
| 57 | Lecture 60 : Built-in Self-Test (Part II) | Download Verified |
| Sl.No | Chapter Name | Hindi |
|---|---|---|
| 1 | Lecture 01: Introduction | Download |
| 2 | Lecture 02: Octal and Hexadecimal Number Systems | Download |
| 3 | Lecture 03: Signed and Unsigned Binary Number Representation | Download |
| 4 | Lecture 04: Binary Addition and Subtraction | Download |
| 5 | Lecture 05: BCD and Gray Code Representations | Download |
| 6 | Lecture 06: Error Detection and Correction | Download |
| 7 | Lecture 07: Logic Gates | Download |
| 8 | Lecture 08: Logic Families to Implement Gates | Download |
| 9 | Lecture 09: Emerging Technologies (Part I) | Download |
| 10 | Lecture 10: Emerging Technologies (Part II) | Download |
| 11 | Lecture 11 : Switching Algebra | Download |
| 12 | Lecture 12 : Algebraic Manipulation | Download |
| 13 | Lecture 13 : Properties of Switching Functions | Download |
| 14 | Lecture 14 : Obtaining Canonical Representations of Functions | Download |
| 15 | Lecture 15 : Functional Completeness | Download |
| 16 | Lecture 16: Minimization Using Karnaugh Maps (Part I) | Download |
| 17 | Lecture 17: Minimization Using Karnaugh Maps (Part II) | Download |
| 18 | Lecture 21: Design of Adders (Part I) | Download |
| 19 | Lecture 22: Design of Adders (Part II) | Download |
| 20 | Lecture 23: Design of Adders (Part III) | Download |
| 21 | Lecture 24: Logic Design(Part I) | Download |
| 22 | Lecture 25: Logic Design(Part II) | Download |
| 23 | Lecture 26: Logic Design(Part III) | Download |
| 24 | Lecture 27: Binary Decision Diagrams (Part I) | Download |
| 25 | Lecture 28: Binary Decision Diagrams (Part II) | Download |
| 26 | Lecture 29: Logic Design using AND-EXOR Network | Download |
| 27 | Lecture 30: Threshold Logic and Threshold Gates | Download |
| 28 | Lecture 31: Latches and Flip-Flops (Part I) | Download |
| 29 | Lecture 32: Latches and Flip-Flops (Part II) | Download |
| 30 | Lecture 33: Latches and Flip-Flops (Part III) | Download |
| 31 | Lecture 34: Clocking and Timing (Part I) | Download |
| 32 | Lecture 35: Clocking and Timing (Part II) | Download |
| 33 | Lecture 36: Synthesis of Synchronous Sequential Circuits (Part I) | Download |
| 34 | Lecture 37: Synthesis of Synchronous Sequential Circuits (Part II) | Download |
| 35 | Lecture 38: Synthesis of Synchronous Sequential Circuits (Part III) | Download |
| 36 | Lecture 39: Synthesis of Synchronous Sequential Circuits (Part IV) | Download |
| 37 | Lecture 40: Minimization of Finite State Machines (Part I) | Download |
| 38 | Lecture 41: Minimization of Finite State Machines (Part II) | Download |
| 39 | Lecture 42: Design of Registers (Part I) | Download |
| 40 | Lecture 43: Design of Registers (Part II) | Download |
| 41 | Lecture 44: Design of Registers (Part III) | Download |
| 42 | Lecture 45: Design of Counters (Part I) | Download |
| 43 | Lecture 46: Design of Counters (Part II) | Download |
| 44 | Lecture 47: Digital-to-Analog Converter (Part I) | Download |
| 45 | Lecture 48: Digital-to-Analog Converter (Part II) | Download |
| 46 | Lecture 49: Analog-to-Digital Converter (Part I) | Download |
| 47 | Lecture 50: Analog-to-Digital Converter (Part II) | Download |
| 48 | Lecture 51: Analog-to-Digital Converter (Part III) | Download |
| 49 | Lecture 52: Asynchronous Sequential Circuits (Part I) | Download |
| 50 | Lecture 53: Asynchronous Sequential Circuits (Part II) | Download |
| 51 | Lecture 54: Algorithmic State Machine (ASM) Chart | Download |
| 52 | Lecture 55 : Testing of Digital Circuits | Download |
| 53 | Lecture 56 : Fault Modeling | Download |
| 54 | Lecture 57 : Test Pattern Generation | Download |
| 55 | Lecture 58 : Design for Testability | Download |
| 56 | Lecture 59 : Built-in Self-Test (Part I) | Download |
| 57 | Lecture 60 : Built-in Self-Test (Part II) | Download |
| Sl.No | Chapter Name | Tamil |
|---|---|---|
| 1 | Lecture 01: Introduction | Download |
| 2 | Lecture 02: Octal and Hexadecimal Number Systems | Download |
| 3 | Lecture 03: Signed and Unsigned Binary Number Representation | Download |
| 4 | Lecture 04: Binary Addition and Subtraction | Download |
| 5 | Lecture 05: BCD and Gray Code Representations | Download |
| 6 | Lecture 06: Error Detection and Correction | Download |
| 7 | Lecture 07: Logic Gates | Download |
| 8 | Lecture 08: Logic Families to Implement Gates | Download |
| 9 | Lecture 09: Emerging Technologies (Part I) | Download |
| 10 | Lecture 10: Emerging Technologies (Part II) | Download |
| 11 | Lecture 11 : Switching Algebra | Download |
| 12 | Lecture 12 : Algebraic Manipulation | Download |
| 13 | Lecture 13 : Properties of Switching Functions | Download |
| 14 | Lecture 14 : Obtaining Canonical Representations of Functions | Download |
| 15 | Lecture 15 : Functional Completeness | Download |
| 16 | Lecture 16: Minimization Using Karnaugh Maps (Part I) | Download |
| 17 | Lecture 17: Minimization Using Karnaugh Maps (Part II) | Download |
| 18 | Lecture 21: Design of Adders (Part I) | Download |
| 19 | Lecture 22: Design of Adders (Part II) | Download |
| 20 | Lecture 23: Design of Adders (Part III) | Download |
| 21 | Lecture 24: Logic Design(Part I) | Download |
| 22 | Lecture 25: Logic Design(Part II) | Download |
| 23 | Lecture 26: Logic Design(Part III) | Download |
| 24 | Lecture 27: Binary Decision Diagrams (Part I) | Download |
| 25 | Lecture 28: Binary Decision Diagrams (Part II) | Download |
| 26 | Lecture 29: Logic Design using AND-EXOR Network | Download |
| 27 | Lecture 30: Threshold Logic and Threshold Gates | Download |
| 28 | Lecture 31: Latches and Flip-Flops (Part I) | Download |
| 29 | Lecture 32: Latches and Flip-Flops (Part II) | Download |
| 30 | Lecture 33: Latches and Flip-Flops (Part III) | Download |
| 31 | Lecture 34: Clocking and Timing (Part I) | Download |
| 32 | Lecture 35: Clocking and Timing (Part II) | Download |
| 33 | Lecture 36: Synthesis of Synchronous Sequential Circuits (Part I) | Download |
| 34 | Lecture 37: Synthesis of Synchronous Sequential Circuits (Part II) | Download |
| 35 | Lecture 38: Synthesis of Synchronous Sequential Circuits (Part III) | Download |
| 36 | Lecture 39: Synthesis of Synchronous Sequential Circuits (Part IV) | Download |
| 37 | Lecture 40: Minimization of Finite State Machines (Part I) | Download |
| 38 | Lecture 41: Minimization of Finite State Machines (Part II) | Download |
| 39 | Lecture 42: Design of Registers (Part I) | Download |
| 40 | Lecture 43: Design of Registers (Part II) | Download |
| 41 | Lecture 44: Design of Registers (Part III) | Download |
| 42 | Lecture 45: Design of Counters (Part I) | Download |
| 43 | Lecture 46: Design of Counters (Part II) | Download |
| 44 | Lecture 47: Digital-to-Analog Converter (Part I) | Download |
| 45 | Lecture 48: Digital-to-Analog Converter (Part II) | Download |
| 46 | Lecture 49: Analog-to-Digital Converter (Part I) | Download |
| 47 | Lecture 50: Analog-to-Digital Converter (Part II) | Download |
| 48 | Lecture 51: Analog-to-Digital Converter (Part III) | Download |
| 49 | Lecture 52: Asynchronous Sequential Circuits (Part I) | Download |
| 50 | Lecture 53: Asynchronous Sequential Circuits (Part II) | Download |
| 51 | Lecture 54: Algorithmic State Machine (ASM) Chart | Download |
| 52 | Lecture 55 : Testing of Digital Circuits | Download |
| 53 | Lecture 56 : Fault Modeling | Download |
| 54 | Lecture 57 : Test Pattern Generation | Download |
| 55 | Lecture 58 : Design for Testability | Download |
| 56 | Lecture 59 : Built-in Self-Test (Part I) | Download |
| 57 | Lecture 60 : Built-in Self-Test (Part II) | Download |
| Sl.No | Chapter Name | Telugu |
|---|---|---|
| 1 | Lecture 01: Introduction | Download |
| 2 | Lecture 02: Octal and Hexadecimal Number Systems | Download |
| 3 | Lecture 03: Signed and Unsigned Binary Number Representation | Download |
| 4 | Lecture 04: Binary Addition and Subtraction | Download |
| 5 | Lecture 05: BCD and Gray Code Representations | Download |
| 6 | Lecture 06: Error Detection and Correction | Download |
| 7 | Lecture 07: Logic Gates | Download |
| 8 | Lecture 08: Logic Families to Implement Gates | Download |
| 9 | Lecture 09: Emerging Technologies (Part I) | Download |
| 10 | Lecture 10: Emerging Technologies (Part II) | Download |
| 11 | Lecture 11 : Switching Algebra | Download |
| 12 | Lecture 12 : Algebraic Manipulation | Download |
| 13 | Lecture 13 : Properties of Switching Functions | Download |
| 14 | Lecture 14 : Obtaining Canonical Representations of Functions | Download |
| 15 | Lecture 15 : Functional Completeness | Download |
| 16 | Lecture 16: Minimization Using Karnaugh Maps (Part I) | Download |
| 17 | Lecture 17: Minimization Using Karnaugh Maps (Part II) | Download |
| 18 | Lecture 21: Design of Adders (Part I) | Download |
| 19 | Lecture 22: Design of Adders (Part II) | Download |
| 20 | Lecture 23: Design of Adders (Part III) | Download |
| 21 | Lecture 24: Logic Design(Part I) | Download |
| 22 | Lecture 25: Logic Design(Part II) | Download |
| 23 | Lecture 26: Logic Design(Part III) | Download |
| 24 | Lecture 27: Binary Decision Diagrams (Part I) | Download |
| 25 | Lecture 28: Binary Decision Diagrams (Part II) | Download |
| 26 | Lecture 29: Logic Design using AND-EXOR Network | Download |
| 27 | Lecture 30: Threshold Logic and Threshold Gates | Download |
| 28 | Lecture 31: Latches and Flip-Flops (Part I) | Download |
| 29 | Lecture 32: Latches and Flip-Flops (Part II) | Download |
| 30 | Lecture 33: Latches and Flip-Flops (Part III) | Download |
| 31 | Lecture 34: Clocking and Timing (Part I) | Download |
| 32 | Lecture 35: Clocking and Timing (Part II) | Download |
| 33 | Lecture 36: Synthesis of Synchronous Sequential Circuits (Part I) | Download |
| 34 | Lecture 37: Synthesis of Synchronous Sequential Circuits (Part II) | Download |
| 35 | Lecture 38: Synthesis of Synchronous Sequential Circuits (Part III) | Download |
| 36 | Lecture 39: Synthesis of Synchronous Sequential Circuits (Part IV) | Download |
| 37 | Lecture 40: Minimization of Finite State Machines (Part I) | Download |
| 38 | Lecture 41: Minimization of Finite State Machines (Part II) | Download |
| 39 | Lecture 42: Design of Registers (Part I) | Download |
| 40 | Lecture 43: Design of Registers (Part II) | Download |
| 41 | Lecture 44: Design of Registers (Part III) | Download |
| 42 | Lecture 45: Design of Counters (Part I) | Download |
| 43 | Lecture 46: Design of Counters (Part II) | Download |
| 44 | Lecture 47: Digital-to-Analog Converter (Part I) | Download |
| 45 | Lecture 48: Digital-to-Analog Converter (Part II) | Download |
| 46 | Lecture 49: Analog-to-Digital Converter (Part I) | Download |
| 47 | Lecture 50: Analog-to-Digital Converter (Part II) | Download |
| 48 | Lecture 51: Analog-to-Digital Converter (Part III) | Download |
| 49 | Lecture 52: Asynchronous Sequential Circuits (Part I) | Download |
| 50 | Lecture 53: Asynchronous Sequential Circuits (Part II) | Download |
| 51 | Lecture 54: Algorithmic State Machine (ASM) Chart | Download |
| 52 | Lecture 55 : Testing of Digital Circuits | Download |
| 53 | Lecture 56 : Fault Modeling | Download |
| 54 | Lecture 57 : Test Pattern Generation | Download |
| 55 | Lecture 58 : Design for Testability | Download |
| 56 | Lecture 59 : Built-in Self-Test (Part I) | Download |
| 57 | Lecture 60 : Built-in Self-Test (Part II) | Download |