| Module Name | Download |
|---|---|
| noc20_cs14_assigment_1 | noc20_cs14_assigment_1 |
| noc20_cs14_assigment_10 | noc20_cs14_assigment_10 |
| noc20_cs14_assigment_11 | noc20_cs14_assigment_11 |
| noc20_cs14_assigment_12 | noc20_cs14_assigment_12 |
| noc20_cs14_assigment_13 | noc20_cs14_assigment_13 |
| noc20_cs14_assigment_2 | noc20_cs14_assigment_2 |
| noc20_cs14_assigment_3 | noc20_cs14_assigment_3 |
| noc20_cs14_assigment_4 | noc20_cs14_assigment_4 |
| noc20_cs14_assigment_5 | noc20_cs14_assigment_5 |
| noc20_cs14_assigment_6 | noc20_cs14_assigment_6 |
| noc20_cs14_assigment_7 | noc20_cs14_assigment_7 |
| noc20_cs14_assigment_8 | noc20_cs14_assigment_8 |
| noc20_cs14_assigment_9 | noc20_cs14_assigment_9 |
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | Lecture 1: Introduction | Download |
| 2 | Lecture 2: Processors | Download |
| 3 | Lecture 3: General Purpose and ASIPs Processor | Download |
| 4 | Lecture 4: Designing a Single Purpose Processor | Download |
| 5 | Lecture 5: Optimization Issues | Download |
| 6 | Lecture 6: Introduction to FPFA | Download |
| 7 | Lecture 7: FPGA Contd. | Download |
| 8 | Lecture 8: Behaviour Synthesis on FPGA using VHDL | Download |
| 9 | Lecture 9: Tutorial - I | Download |
| 10 | Lecture 10 : Tutorial - II | Download |
| 11 | Lecture 11: Tutorial - III | Download |
| 12 | Lecture 12: Tutorial - IV | Download |
| 13 | Lecture 13: Sensors and Signals | Download |
| 14 | Lecture 14: Discretization of Signals and A/D Converter | Download |
| 15 | Lecture 15: Quantization Noise, SNR and D/A Converter | Download |
| 16 | Lecture 16: Arduino Uno | Download |
| 17 | Lecture 17: Arduino Uno (Contd.), Serial Communication and Timer | Download |
| 18 | Lecture 18: Controller Design using Arduino | Download |
| 19 | Lecture 19: Tutorial - V | Download |
| 20 | Lecture 20:Power Aware Embedded System - I | Download |
| 21 | Lecture 21: Power Aware Embedded System - II | Download |
| 22 | Lecture 22: SD and DD Algorithm | Download |
| 23 | Lecture 23: Parallel Operations and VLIW | Download |
| 24 | Lecture 24: Code Efficiency | Download |
| 25 | Lecture 25: DSP Application and Address Generation Unit | Download |
| 26 | Lecture 26: Real Time O.S - I | Download |
| 27 | Lecture 27: Real Time O.S - II | Download |
| 28 | Lecture 28: RMS Algorithm | Download |
| 29 | Lecture 29 : EDF Algorithm and Resource Constraint Issue | Download |
| 30 | Lecture 30 : Priority Inversion and Priority Inheritance Protocol | Download |
| 31 | Lecture 31 : Modeling and Specification - I | Download |
| 32 | Lecture 32 : Modeling and Specification - II | Download |
| 33 | Lecture 33 : FSM and Statechart | Download |
| 34 | Lecture 34 : Statechart and Statemate Semantics | Download |
| 35 | Lecture 35 : Statecharts (Contd.) | Download |
| 36 | Lecture 36 : Program State Machines | Download |
| 37 | Lecture 37 : SDL | Download |
| 38 | Lecture 38 : Data Flow Model - I | Download |
| 39 | Lecture 39 : Data Flow Model - II | Download |
| 40 | Lecture 40 : Hardware Synthesis - I | Download |
| 41 | Lecture 41 : Hardware Synthesis - II | Download |
| 42 | Lecture 42 : Scheduling | Download |
| 43 | Lecture 43 : Digital Camera Design | Download |
| 44 | Lecture 44 : Digital Camera - Iterative Design | Download |
| 45 | Lecture 45 : HW-SW Partitioning | Download |
| 46 | Lecture 46 : Optimization - I | Download |
| 47 | Lecture 47 : Optimization - II | Download |
| 48 | Lecture 48 : Simulation | Download |
| 49 | Lecture 49 : Formal Verification | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Lecture 1: Introduction | Download To be verified |
| 2 | Lecture 2: Processors | Download To be verified |
| 3 | Lecture 3: General Purpose and ASIPs Processor | Download To be verified |
| 4 | Lecture 4: Designing a Single Purpose Processor | Download To be verified |
| 5 | Lecture 5: Optimization Issues | Download To be verified |
| 6 | Lecture 6: Introduction to FPFA | Download To be verified |
| 7 | Lecture 7: FPGA Contd. | Download To be verified |
| 8 | Lecture 8: Behaviour Synthesis on FPGA using VHDL | Download To be verified |
| 9 | Lecture 9: Tutorial - I | Download To be verified |
| 10 | Lecture 10 : Tutorial - II | Download To be verified |
| 11 | Lecture 11: Tutorial - III | Download To be verified |
| 12 | Lecture 12: Tutorial - IV | Download To be verified |
| 13 | Lecture 13: Sensors and Signals | Download To be verified |
| 14 | Lecture 14: Discretization of Signals and A/D Converter | Download To be verified |
| 15 | Lecture 15: Quantization Noise, SNR and D/A Converter | Download To be verified |
| 16 | Lecture 16: Arduino Uno | Download To be verified |
| 17 | Lecture 17: Arduino Uno (Contd.), Serial Communication and Timer | Download To be verified |
| 18 | Lecture 18: Controller Design using Arduino | Download To be verified |
| 19 | Lecture 19: Tutorial - V | Download To be verified |
| 20 | Lecture 20:Power Aware Embedded System - I | Download To be verified |
| 21 | Lecture 21: Power Aware Embedded System - II | Download To be verified |
| 22 | Lecture 22: SD and DD Algorithm | Download To be verified |
| 23 | Lecture 23: Parallel Operations and VLIW | Download To be verified |
| 24 | Lecture 24: Code Efficiency | Download To be verified |
| 25 | Lecture 25: DSP Application and Address Generation Unit | Download To be verified |
| 26 | Lecture 26: Real Time O.S - I | Download To be verified |
| 27 | Lecture 27: Real Time O.S - II | Download To be verified |
| 28 | Lecture 28: RMS Algorithm | Download To be verified |
| 29 | Lecture 29 : EDF Algorithm and Resource Constraint Issue | Download To be verified |
| 30 | Lecture 30 : Priority Inversion and Priority Inheritance Protocol | Download To be verified |
| 31 | Lecture 31 : Modeling and Specification - I | Download To be verified |
| 32 | Lecture 32 : Modeling and Specification - II | Download To be verified |
| 33 | Lecture 33 : FSM and Statechart | Download To be verified |
| 34 | Lecture 34 : Statechart and Statemate Semantics | Download To be verified |
| 35 | Lecture 35 : Statecharts (Contd.) | Download To be verified |
| 36 | Lecture 36 : Program State Machines | Download To be verified |
| 37 | Lecture 37 : SDL | Download To be verified |
| 38 | Lecture 38 : Data Flow Model - I | Download To be verified |
| 39 | Lecture 39 : Data Flow Model - II | Download To be verified |
| 40 | Lecture 40 : Hardware Synthesis - I | Download To be verified |
| 41 | Lecture 41 : Hardware Synthesis - II | Download To be verified |
| 42 | Lecture 42 : Scheduling | Download To be verified |
| 43 | Lecture 43 : Digital Camera Design | Download To be verified |
| 44 | Lecture 44 : Digital Camera - Iterative Design | Download To be verified |
| 45 | Lecture 45 : HW-SW Partitioning | Download To be verified |
| 46 | Lecture 46 : Optimization - I | Download To be verified |
| 47 | Lecture 47 : Optimization - II | Download To be verified |
| 48 | Lecture 48 : Simulation | Download To be verified |
| 49 | Lecture 49 : Formal Verification | Download To be verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |